In the physical implementation of a digital circuit on a chip 10, such as is illustrated in FIG. 1, a network 12 needs to be provided to distribute copies of the clock signal to the clocked components (e.g. registers, flip-flops, latches and other logic devices) or groups of clocked components 14 distributed throughout the circuit. The network that performs this function is referred to as clock distribution network or a clocktree. It is referred to as a tree because of the hierarchical character of its structure, with multiple levels of branching.
In large circuits with many elements, designing the clocktree can be a very challenging part of the overall circuit design process. For example, in a chip that has 700,000 placeable elements, 10% of those elements (i.e., 70,000 elements) may need a copy of the clock signal. Just getting the clock signal to that many elements can be a challenge in itself. Moreover, as the size of the devices has decreased, as the areas of the integrated circuit chips and the component counts have increased, the quality of the distributed clock signal has become one of the primary factors limiting circuit performance.
One challenge in designing a clock distribution network is due in part to the component and interconnect parasitic capacitances and resistances that cause the clock signal that is being distributed throughout the network to experience different delays. So, one set of clocked components located in one area of the circuit may receive the clock signal later than other clocked components elsewhere in the circuit. These differences in the times at which the clock signals reach the various components are referred to as clock timing skews. If excessively large, the skews can cause the circuit to operate improperly or not operate at all. So, the goal of many design processes is to reduce these timing skews to zero or, more practically, to a level that is below some minimum specified target value.
The creation of the clocktree has become a major bottleneck in engineering a large ASIC (Application Specific Integrated Circuit). In current practice, an engineer uses a clocktree synthesis design tool to initially design the clocktree. During this stage, clocktree synthesis is initially performed with buffers and large inverters. After the initial design is completed, the designer, usually with the aid of a timing analysis tool, measures the skews among various locations on the tree at the “worst case” corners. Invariably, the skews are unsatisfactory in some number of the branches of the clocktree and the timing analysis tool identifies those branches. A lengthy and tedious iterative process usually ensues during which various “tweaks” or adjustments in layout, buffers, fanout, etc. are made and the resultant skews measured again. After the skews are made satisfactory at the worst-case corner, “best case” skews must be checked and further iterations often ensue. Frequently this process must be repeated again and again, eventually becoming tedious and exasperating. It is not unusual to reach a point in the clocktree design process at which the clocktree must be removed and the design effort begun anew.
One frequently employed option in the design process is to measure what is referred to as the pre-route timing before the routing is performed. If this is done, timing adjustments are usually made to reduce any timing skews that are excessive. Just as the post routing timing adjustment process is iterative, so is the pre-route timing adjustment process. And similarly this phase can also consume a lot of time.
As the circuits have become larger and more complex, the time required to design the clock distribution network has increased significantly. Indeed, the above-described clocktree trial-and-error process can add a month or more to the project and even then the final result is sometimes so sub-optimum that chip performance must be downgraded.